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L6180 L6181
OCTAL LINE RECEIVER
ADVANCE DATA
OCTAL LINE RECEIVER FOR: - EIA STD RS232D RS423A RS422A - CCIT V.10 V.11 V.28 X.26 NO EXTERNAL COMPONENTS INPUT FAIL SAFING CAPABILITY HIGH CROSSTALK REJECTION L6180 DATA RATE < 100KBIT/S L6181 DATA RATE < 1MBIT/S 50V EOS OUTPUT PROTECTION DESCRIPTION L6180/1 is an octal line receiver in a plastic DIP or PLCC designed to meet a wide range of digital communications requirements as outlined in the EIA standards RS232A without additional components, as well as the low speed applications of RS422A. BLOCK DIAGRAM
DIP 28
PLCC 28
ORDERING NUMBER: L6180A DIP 28 L6180D PLCC28 L6181A DIP 28 L6181D PLCC28
The receiver meets the CCIT recommendations V.10, V.11, X.26 and V.28 low speed applications (below 100KBS). A low pass filter on the input starts to roll off at a frequency of 100KHz.
October 1993
1/10
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6180 - L6181
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VDD VSS CRR VID Ptot IOS t Top Tstg Supply Voltage Supply Voltage Logic Supply Voltage Common Mode Range Differential Input Voltage Power Dissipation (PLCC 28) Power Dissipation (DIP 28) Output Sink Current Output Short Circuit Time Operating Free Air Temperature Range Storage Temperature Range ESD Input Transient Protection Parameter Value 7 13.5 -13.5 15 25 800 1200 50 1 0 to 70 -65 to 150 2KV max ESD 50J 50V min EOS 100s Unit V V V V V mW mW mA sec C C
PIN CONNECTIONS (Top views)
DIP28
PLCC28
2/10
L6180 - L6181
ELECTRICAL CHARACTERISTICS (VCC = 5V 5%; VCM = -7 to 7V; Tamb = 0 to 70C; VSS = -9 to 13.5V; VDD = 9 to 13.5V; unless otherwise specified.)
Symbol VIN Parameter Input Current Test Condition (See Fig.1 and note2) VCC = 0 to 5.25V; VSS, VDD = 0 to 13.5V VIN = - 10 to 10V VIN = - 15 to 15V VIA or VIB = 3 to 15V; (see fig.1) [(VIA or VIN) -VIOC] RI = IIN VFS VOH VOL VIT2 IIH2 IIH1 VH VIOC1 Failsafe Output Voltage High Level Output Voltage Low Level Output Voltage VIOH Comparator Threshold Voltage High Operating Threshold Voltage Low Operating Threshold Voltage Input Hysteresis Voltage Open Circuit Input Voltage IO = -440A (See Fig.3) VCC = 4.75V; VID = -1V; IOH = -440A VCC = 5.25V; VID = -1V; IOL = 2mA (See Fig.4) VOL = 0.4V; IOL = 2mA; (See Fig.4) VOH = 2.7V; IO = -440A (See Fig.4) |VTH2 - VTH1| Measured in accordance with V.28 and RS-232D (see note 4 and 7) Measured in presence of AC Input Signal (see note 7) VCC = 5.25V; VO = 0; VID = 1V; (see note 5) (see Figure 7 and note 11) VCC = 4.75V to 5.25V; (see note 6) Vdd = 9 to 3.5V; (see note 6) VSS = -9 to 13.5V; (see note 6) VCC = 5.25V; VO = 0; VID = 1V; (see note 5) RL = 390; CL = 50pF; |VIN = 1V|; (see fig 5 test Circuit Fig. 6) RL = 390; CL = 50pF; |VIN = 1V|; (see fig 5 test Circuit Fig. 6) (see note 7A) (see note 7B) RL = 390; CL = 50pF; |VIN| = 1V;(see fig. 5; Test Circuit Fig. 6) RL = 390; CL = 50pF; |VIN| = 1V;(see fig. 5; Test Circuit Fig. 6) VIN = 200mVpp; (see fig. 8 and note 7; 200 0 500 20 0 3.5 20 1.8 -25 -125 50 0.6 2.2 2.7 2.7 0.4 2.6 -75 -175 150 2 V V V V mV mV mV V 3 Min. Typ. Max. Unit
3 4.25 7
mA mA K
RI
Input Resistance
VIOCH IOS VIBV CI VCC Vdd VSS IOS Tplh
Open Circuit Input Voltage Open Short Circuit Current Input for Balance Test Input Capacitance Supply Current Supply Current Supplyt Current Open Short Circuit Current Propagation Delay Low to High
4
4.5 100 0.4 100 100 30 30 100 1500
V mA V pF mA mA mA mA ns
Tphl
Propagation Delay Low to High
0
1500
ns
VIOCH VIOCL Vist
Delay VIOCL to VIOCH Switching Delay VIOCH to VIOCL Switching |Tplh - Tphl|
5
ms ms ns
TSKEW1
Skew between rec's in PKg Tp (1) hl/1h - Tp (2) hl/1h Frequency Accepted (Receiver will Output)
0
300
ns
fA
100
KHz
3/10
L6180 - L6181
ELECTRICAL CHARACTERISTICS (VCC = 5V 5%; VCM = -7 to 7V; Tamb = 0 to 70C; VSS = -9 to 13.5V; VDD = 9 to 13.5V; unless otherwise specified.)
Symbol fR Parameter Frequency Rejected (No Receiver Output) Test Condition VIN = 2Vpp; (see fig. 8 and note 7) Min. Typ. 5 Max. Unit MHz
Note: 1) The algebric convention, where the less positive (more negative) is designed the minimum 2) With the voltage VIA or (VIB) ranging between 15V, while VIB or (VIA) is open or grounded, the resultant input current IIA or (IIB) shall remain within the shaded region shown in the graph in Fig.1. 3) Either Point B' or Point A' is grounded in Figure 1 4) VICC measured from grounded to (+) input with (-) input grounded VICC measured from grounded to (+) input with (-) input grounded 5) Not more than one output should be shorted at a time and for less than 1 seond 6) The sum of the product of the maximum supply currents and voltages cannot exceed themaximum power dissipation 7) 8) A: The conditions for the inpit switching from VIOCL to VIOCH mode is: Vid in start bit "spacing condition"for less than TpVioch (5ms). B: The conditions for the input switching from VIOCH to VIOCL mode is: Vid > WW2 for greater than TpVIOCL (200ms) An example of a frequency response plot meeting the rejection/acceptance requirements is provided in figure 8.
LINE TRANSIENT IMMUNITY (Considering the following cases; powered ON, Powered OFF-LOW impedance power supply and powered OFF-HIGH impedance supply)
Symbol ESD EOS
Note: 9) All pins are required to withstand this parameters. 10) Input pins are required to withstand fig.2 without any degradation to the circuit. 11) The balance test requirement can be met by use of a current limit circuit which reduces the input bias current Iib (see figure 7) for input voltages below a threshold voltage given by (Iib x 1K) - 400mV.
Parameter Static Stress
Test Condition tested per MIL-STD-883 (see note 9) transient pulse both polarities for 100s (see note 9 and Fig. 2)
Min. 2 50
Typ.
Max.
Unit KV V
Figure 1: Input Current Voltage Mesurements
4/10
L6180 - L6181
Figure 2: EOS Requiremets
Figure 3: Output Failsafing
The output assumes a logic "1"under the following conditions, (see figure 3) 1 Both inputs open 2 Both inputs shorted 3 Signal Opencircuit 3a Common grounded, signal open circuit 4 Common open, generator powered-on 5 Generatorpowered-down (see note 7) 6 Common open, generator powered-down 6a Signal grounded, common open, generator powered-down 7 Less than 250mVpp differential signal
5/10
L6180 - L6181
Figure 4: Threshold voltage definition
Figure 5: PropagationDelay
Figure 6: AC Test Circuit
6/10
L6180 - L6181
Figure 7: Receiver input Balance Measurement
Figure 8: High Frequency Signal Rejection INPUT BALANCE MEASUREMENT The balance of the receiver input voltage-current characteristics and bias voltages shall be such that the receiver will remain in the intended binary state when a differential voltage Vi of 400mV is applied through 500 1% to each input terminal, as shown above, and Vcm is varied between -7 and +7V. When the polarity of Vi is reversed, the opposite binary state shall be maintained under the same conditions. Maintain input balance with input B common with another receiver. The voltage input (VIN) rejection is checked at the center point between the High Operating Threshold (Vth2) and the Low OperatingThreshold (Vth1)
7/10
L6180 - L6181
PLCC28 PACKAGE MECHANICAL DATA
DIM. MIN. A B D D1 D2 E e e3 F F1 G M M1 1.24 1.143 12.32 11.43 4.2 2.29 0.51 9.91 1.27 7.62 0.46 0.71 0.101 0.049 0.045 10.92 mm TYP. MAX. 12.57 11.58 4.57 3.04 MIN. 0.485 0.450 0.165 0.090 0.020 0.390 0.050 0.300 0.018 0.028 0.004 0.430 inch TYP. MAX. 0.495 0.456 0.180 0.120
8/10
L6180 - L6181
DIP28 PACKAGE MECHANICAL DATA
DIM. MIN. a1 b b1 b2 D E e e3 F I L 4.445 3.3 15.2 2.54 33.02 14.1 0.175 0.130 0.23 1.27 37.34 16.68 0.598 0.100 1.300 0.555 mm TYP. 0.63 0.45 0.31 0.009 0.050 1.470 0.657 MAX. MIN. inch TYP. 0.025 0.018 0.012 MAX.
9/10
L6180 - L6181
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore -
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